Bias-Stress Effect in Pentacene Organic Thin-Film Transistors

Publication Type:

Journal Article


IEEE Trans. Electron Devices,, Volume 57, Issue 5, p.1003-1008 (2010)




2010, 2013 and earlier, bias-stress effect, carrier density, carrier trapping rate equation, channel carrier density, Circuits, Dielectrics, drain bias stress measurements, electron traps, Equations, Field-effect transistor (FETs), gate bias stress measurements, integrated pentacene organic thin-film transistors, organic compounds, organic field effect transistors, Organic thin film transistors, Pentacene, reliability, Sensor arrays, stability, stress, stress measurement, thin film transistors, thin-film transistors (TFTs), Voltage


The effects of bias stress in integrated pentacene organic transistors are studied and modeled for different stress conditions. It is found that the
effects of bias stress can be expressed in terms of the shift in applied
gate voltage ¿V for a given current. An empirical equation describing ¿V
in terms of different gate and drain bias stress measurements and stress
times is presented and verified. In the measured devices, ¿V saturates at
14 V, independent of the gate bias-stress condition. A model based on
carrier trapping rate equation that accounts for this ¿V saturation is
developed. The model suggests that the ¿V saturation is due to the small
density of traps compared to the channel carrier density.